The present invention relates to a semiconductor device and more particularly, to a semiconductor device such as a Rambus DRAM (Dynamic Random Access Memory) or the like which may have a plurality of operational frequencies with which circuit operation may be implemented in a manner appropriate to each operational frequency.
Semiconductor devices may be specifically guaranteed by a specification to reliably function at a plurality of operational frequencies. One such type of a device is a Rambus Dynamic Random Access Memory (RDRAM).
Referring now to FIG. 1, a block schematic diagram of a Rambus DRAM is set forth and given the general reference character 100.
Rambus DRAM 100 includes a high-speed interface section 110 and a core section 120. High-speed interface section 110 has a high frequency data transfer speed and includes a register for setting the operating frequency. The phase difference between the input and output signals of the high-speed interface section 110 is compensated by setting a desired operating frequency in the register. This can help make high frequency operation possible. Core section 120 is a DRAM including banks, which have a protocol that is compatible for data transfer via high-speed interface section 110. The core section 120 operates at the same operational speed as a conventional DRAM.
However, with the Rambus DRAM 100 described above, the power supply voltage of core section 120 is kept constant irrespective of the selected operating frequency set in the register of the high-speed interface section 110. The power supply voltage is typically selected so that the most appropriate operating condition can be adequately achieved. Generally, the operating speed of a circuit is dependent upon the power supply voltage. The power supply voltage for core section 120 is typically set to allow the maximum allowable operating frequency because the greater the power supply voltage the greater the operating speed becomes.
However, when the operating frequency becomes lower, high operational speed for core section 120 may no longer be necessary and it may no longer be necessary to keep the power supply voltage at a high level. Also, current consumption is dependent upon the power supply voltage. The higher the power supply voltage, the higher the current consumption. Accordingly, if the power supply voltage is kept higher than necessary when the operating frequency is low, excessive current is consumed.
It may be considered to lower the voltage of the internal power supply for core section 120 when the operating frequency is low in order to decrease current consumption. However, if the internal power supply voltage is reduced, the relative timing relationship between various signals may not be maintained. This is because propagation delay of signals in various circuits in core section 120 may vary with respect to voltage variations. When these signals have critical timings, functionality may be compromised. For this reason it is not feasible to simply lower the voltage of the internal power supply in core section 120.
In view of the above discussion, it would be desirable to provide a semiconductor device, which can change the internal power supply voltage according to the operating frequency while maintaining relative timing relationships between various signals. It would also be desirable to suppress excess current consumption in a semiconductor device as the operating frequency decreased.
According to the embodiments of the present invention, a semiconductor device having an internal voltage, signal timing, and logic current supply determined by a desired operating frequency is disclosed. The semiconductor device may include a register that may store a code value received externally during a code setting operation. A decoder may decode the code value and provide decoded signals to an internal power source circuit, an internal logic circuit system, and a sense amp system. The internal power source circuit may generate a power supply voltage based on the code value. The internal logic circuit system may be coupled to receive the power supply voltage and may generate a signal delay based on the code value. The sense amp system may be coupled to receive the power supply voltage and may have a operating current based on the code value. In this way, signal timings may be improved and power consumption may be reduced.
According to one aspect of the embodiments, a semiconductor device may include a code setting section having a code, which may indicate a desired operating frequency. A power supply voltage section may select a power supply voltage level based on the code. A delay section may select a signal delay amount based on the code.
According to another aspect of the embodiments, the semiconductor device may include a current providing section, which selects a current value based on the code.
According to another aspect of the embodiments, the semiconductor device may include a control section coupled to receive the code and provide decoded signals to the power supply voltage section to select the power supply voltage and the delay section to select the delay amount.
According to another aspect of the embodiments, the power supply voltage section may include a plurality of transfer gates, which select between a plurality of power supply voltage levels based on the code value.
According to another aspect of the embodiments, the power supply voltage section may include a reference voltage generation section. The plurality of transfer gates may select between a plurality of power supply voltage levels by selecting a reference voltage based on the code value.
According to another aspect of the embodiments, the semiconductor device may include a control section coupled to receive the code and provide decoded signals to the power supply voltage section to select the power supply voltage level. Each of the plurality of transfer gates may include a transfer gate control terminal for controlling a transfer gate controllable impedance path. The power supply voltage section may include a switch section which couples the decoded signals to selected transfer gate control terminals while setting unselected transfer gate control terminals to a predetermined logic level.
According to another aspect of the embodiments, the transfer gate control terminals may be selected by a plurality of programmable devices.
According to another aspect of the embodiments, the transfer gate control terminals may be selected by a mask programmable conductive layer.
According to another aspect of the embodiments, the transfer gate control terminals may be selected by a plurality of programmable devices.
According to another aspect of the embodiments, the code may be externally received during a code setting operation.
According to another aspect of the embodiments, a semiconductor device may include a code setting section storing a code value indicating a desired device operating frequency. A power supply circuit may generate a power supply potential based on the code value. A logic circuit may receive the power supply potential and may modify the timing of a logic signal based on the code value.
According to another aspect of the embodiments, the timing of the logic signal may be determined by configuring a signal propagation delay path in accordance with the code value.
According to another aspect of the embodiments, the logic circuit may include a plurality of delay circuits providing different signal propagation delays. A plurality of switches may select at least one of the plurality of delay circuits based on the code value.
According to another aspect of the embodiments, a control section may be coupled to receive the code value and provide decoded signals coupled to the logic circuit to select at least one of the plurality of delay circuits.
According to another aspect of the embodiments, the logic signal may be a sense amplifier activation signal.
According to another aspect of the embodiments, a semiconductor device may include a code setting section outputting a code value indicating a desired device operating frequency. A power supply circuit may generate a power supply potential based on the code value. A first circuit may be connected to the power supply potential and may have an operating current based on the code value.
According to another aspect of the embodiments, the first circuit may include a plurality of current sources. A plurality of transfer gates may select one of the plurality of current sources based on the code value.
According to another aspect of the embodiments, each of the plurality of current sources includes an IGFET for supplying the operating current to the first circuit.
According to another aspect of the embodiments, the semiconductor device may include a control section coupled to receive the code value and provide decoded signals to the first circuit to select the operating current. The code setting section may include a register storing the code value.
According to another aspect of the embodiments, the first circuit may include a differential amplifier and the semiconductor device may be a semiconductor memory device.